The paper entitled “Speeding-up robustness assessment of HDL models through profiling and multi-level fault injection”, written Ilya Tuzov, David de Andres and Juan Carlos Ruiz has been awarded as Best Paper in LADC 2018.
Luis J. Saiz has presented at LADC 2018 the paper entitled “Correction of Adjacent Errors with Low Redundant Matrix Error Correction Codes” written by Joaquin Gracia-Moran, Luis-J. Saiz-Adalid, Juan-Carlos Baraza-Calvo and Pedro Gil-Vicente.
Juan Carlos Ruiz has presented at LADC 2018 the best paper candidate entitled “Speeding-up robustness assessment of HDL models through profiling and multi-level fault injection”, written Ilya Tuzov, David de Andres and Juan Carlos Ruiz.
The PhD work entitled ““Improving the process of analysis and comparison of results in dependability benchmarking for computer systems”, developed by Miquel Martínez Raga, and directed by David de Andres and Juan Carlos Ruiz has been awarded with a claification of Sobresaliente Cum Laude.
Our PhD student, Miquel Martínez Raga, has succesfully defended his thesis entitled “Improving the process of analysis and comparison of results in dependability benchmarking for computer systems”.
J. Gracia-Morán has presented the paper entitled “Un nuevo Código de Corrección de Errores matricial con baja redundancia“, presented at the Jornadas Sarteco, held in Teruel, 12-14 September, 2018.
David de Andrés has presented the paper entitled “Accurate Robustness Assessment of HDL Models through Iterative Statistical Fault Injection” at EDCC 2018.
This work has been selected as one of the “Distinguished Papers”.
The paper entitled “Simulating the effects of logic faults in implementation-level VITAL-compliant models”, written by Ilya Tuzov, David de Andrés and Juan-Carlos Ruiz has been accepted at Computing journal (Springer). This paper is an extension of the paper entitled “Accurately simulating the effects of faults in VHDL models described at the implementation-level”, awarded as best paper in the EDCC 2017.
Simulation-based fault injection (SBFI) is a well-known technique to assess the dependability of hardware designs specified using Hardware Description Languages (HDL). Although logic faults are usually introduced in models defined at the Register Transfer Level (RTL), most accurate results can be obtained by considering implementation-level ones, which reflect the actual structure and timing of the circuit. These models consist of a list of interconnected technology-specific components (macrocells), provided by vendors and annotated with post-place-and-route delays. Macrocells described in the Very High Speed Integrated Circuit HDL (VHDL) should also comply with the VHDL Initiative Towards Application Specific Integrated Circuit Libraries (VITAL) standard to be interoperable across standard simulators. However, the rigid architecture imposed by VITAL makes that fault injection procedures applied at RTL cannot be used straightforwardly. This work identifies a set of generic operations on VITAL-compliant macrocells that are later used to define how to accurately simulate the effects of common logic fault models. The generality of this proposal is supported by the definition of a platform-specific fault procedure based on these operations. Three embedded processors, implemented using the Xilinx’s toolchain and SIMPRIM library of macrocells, are considered as a case study, which exposes the gap existing between the robustness assessment at both RTL and implementation-level.