Paper accepted at IEEE Access

The paper entitled “Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection”, authored by Luis-J. Saiz-Adalid, Joaquín Gracia-Morán, Daniel Gil-Tomás, J.-Carlos Baraza-Calvo and Pedro-J. Gil-Vicente has been accepted at IEEE Access.

Abstract

Reliable computer systems employ error control codes (ECCs) to protect information from errors. For example, memories are frequently protected using single error correction-double error detection (SEC-DED) codes. ECCs are traditionally designed to minimize the number of redundant bits, as they are added to each word in the whole memory. Nevertheless, using an ECC introduces encoding and decoding latencies, silicon area usage and power consumption. In other computer units, these parameters should be optimized, and redundancy would be less important. For example, protecting registers against errors remains a major concern for deep sub-micron systems due to technology scaling. In this case, an important requirement for register protection is to keep encoding and decoding latencies as short as possible. Ultrafast error control codes achieve very low delays, independently of the word length, increasing the redundancy. This paper summarizes previous works on Ultrafast codes (SEC and SEC-DED), and proposes new codes combining double error detection and adjacent error correction. We have implemented, synthesized and compared different Ultrafast codes with other state-of-the-art fast codes. The results show the validity of the approach, achieving low latencies and a good balance with silicon area and power consumption.

Presentation at Jornadas SARTECO 2019

Last 18 September, J. Gracia-Morán presented the paper entitled “Mejora de un Código de Corrección de Errores para tolerar fallos adyacentes bidimensionales” at the Jornadas SARTECO 2019.

Panel at CARS 2019

Last September, 17th, Juan Carlos Ruiz took part in the panel “Autonomous driving: safety and security issues”, celebrated in the 5th International Workshop on Critical Automotive Applications: Robustness & Safety (CARS 2019), collocated with EDCC 2019 in Naples, Italy.

Presentation at EDCC 2019

Juan Carlos Ruiz has presented the paper entitled Robustness-aware design space exploration by iteratively augmenting and repairing D-optimal designs”, written by Ilya Tuzov, David De Andrés and Juan Carlos Ruiz.

Abstract:

Design space exploration (DSE) is nowadays of utmost importance to implement HW designs with acceptable levels of performance, power consumption, area and dependability (PPAD). Electronic Design Automation (EDA) tools support the transformation of HW description models into technology-dependent implementations. Although designers can influence this process by tuning the parameters offered by EDA toolkits, determining their proper configuration is a complex and very time-consuming DSE problem rarely addressed from a PPAD perspective. On one hand, the spatial and temporal complexity of considered targets and the level of abstraction of their descriptions pose problems for the rapid execution of fault injection campaigns. On the other hand, the multi-level nature of parameters offered by EDA toolkits lead to an explosion of possible configurations to exercise during experimentation. This paper shows how to combine the D-optimal design of experiments with FPGA-based and statistical fault injection to significantly reduce not only the number of such configurations but also the number of faults to inject and the time required to perform each injection. All of this without compromising the statistical significance of results. The proposal is exemplified through the Xilinx Vivado Design Suite, which integrates one of the FPGA-based EDA toolkits most widely-used today in the industry, and the MC8051 IP core, a synthesizable microcontroller from Oregano Systems.

Paper available at Electronics Journal

The paper entitled “Fault Modeling of Graphene Nanoribbon FET Logic Circuits”, written by D. Gil-Tomàs, J. Gracia-Morán, L.J. Saiz-Adalid and P.J. Gil-Vicente, and published by Electronics Journal, is now available here.

 

Paper accepted at Electronics Journal

The paper entitled “Fault Modeling of Graphene Nanoribbon FET Logic Circuits”, written by D. Gil-Tomàs, J. Gracia-Morán, L.J. Saiz-Adalid and P.J. Gil-Vicente has been accepted for publication at Electronics Journal.

Abstract:

Due to the increasing defect rates in highly scaled complementary metal–oxide–semiconductor (CMOS) devices, and the emergence of alternative nanotechnology devices, reliability challenges are of growing importance. Understanding and controlling the fault mechanisms associated with new materials and structures for both transistors and interconnection is a key issue in novel nanodevices. The graphene nanoribbon field-effect transistor (GNR FET) has revealed itself as a promising technology to design emerging research logic circuits, because of its outstanding potential speed and power properties. This work presents a study of fault causes, mechanisms, and models at the device level, as well as their impact on logic circuits based on GNR FETs. From a literature review of fault causes and mechanisms, fault propagation was analyzed, and fault models were derived for device and logic circuit levels. This study may be helpful for the prevention of faults in the design process of graphene nanodevices. In addition, it can help in the design and evaluation of defect- and fault-tolerant nanoarchitectures based on graphene circuits. Results are compared with other emerging devices, such as carbon nanotube (CNT) FET and nanowire (NW) FET.

 

DSN 2020 will be held at UPV

The Fault Tolerant Systems Group (STF) of the Institute ITACA from the UPV will host the next International Conference on Dependable Systems and Networks (DSN), that will be held in Valencia in June 2020.

Over the years, the International Conference on Dependable Systems and Networks has pioneered the fusion between dependability and security research, understanding the need to simultaneously fight against accidental faults, intentional cyber-attacks, design errors, and unexpected operating conditions. These concerns can no longer be tackled in isolation, neither in general IT nor in internet-of-things, cyber-physical systems, autonomous transportation, robotics and application areas.

We hope to see you in Valencia!!

Paper accepted at Jornadas SARTECO 2019

The paper entitled “Mejora de un Código de Corrección de Errores para tolerar fallos adyacentes bidimensionales” written by J. Gracia-Morán, L.J. Saiz-Adalid, D. Gil-Tomás, J.C. Baraza-Calvo and P.J. Gil-Vicente has been accepted at Jornadas SARTECO 2019.

Abstract:

Durante estos últimos años, el desarrollo tecnológico ha permitido aumentar la escala de integración de los circuitos integrados. En particular, este aumento ha posibilitado la creación de sistemas de memoria de gran capacidad. Sin embargo, también ha provocado un incremento en su tasa de fallos, aumentando la probabilidad de que se produzcan Single Cell Upsets (SCUs) o Multiple Cell Upsets (MCUs).
Una posible solución para tolerar estos errores es el uso de Códigos de Corrección de Errores (del inglés Error Correction Codes – ECCs). Dependiendo del ECC introducido, es posible corregir una gran variedad de tipos de errores, teniendo en cuenta que la introducción de un ECC implica una serie de sobrecargas a considerar, sobre todo cuando el ECC se utiliza en aplicaciones empotradas.
En un trabajo anterior presentamos un ECC diseñado para corregir fallos adyacentes, apto para aplicaciones empotradas. En este trabajo se presenta una mejora de este ECC que amplía la cobertura de error frente a fallos adyacentes sin aumentar el número de bits extra necesarios para corregirlos.

Paper accepted at ITACA-WIICT 2019

The paper entitled “Comparison of an Improved Matrix-based Error Correction Code”, written by J. Gracia-Morán, L.J. Saiz-Adalid, D. Gil-Tomás, J.C. Baraza-Calvo and P.J. Gil-Vicente has been accepted in the Workshop on Innovation on Information and Communication Technologies (ITACA-WIICT 2019).

Abstract:

Nowadays, the probability of occurrence of Single Cell Upsets (SCUs) or Multiple Cell Upsets (MCUs) has increased due to the continuous in-crement in the integration scale of CMOS technology, that has provoked an augment in the fault rate. SCUs and MCUs are particularly common in comput-er memory systems. To tolerate errors, it is common the use of Error Correction Codes (ECCs). Nevertheless, when using ECCs, a series of overheads are add-ed: extra bits to detect and/or correct errors, and some area, power consumption and delay overheads of the encoders and decoders circuits.
In order to tolerate MCUs, different approaches have been presented in the lit-erature. Specifically, in this work, we present a complete comparison of differ-ent matrix-based ECCs, some of them recently presented.

Paper accepted at EDCC 2019

The paper entitled “Robustness-aware design space exploration through iterative refinement of D-optimal designs”, written by Ilya Tuzov, David de Andrés and Juan-Carlos Ruiz has been accepted at EDCC 2019.

Abstract:

Design space exploration (DSE) is nowadays of utmost importance to implement HW designs with acceptable levels of performance, power consumption, area and dependability (PPAD).  Electronic Design Automation (EDA) tools support the transformation of HW description models into technology-dependent implementations. Although designers can influence this process by tuning the parameters offered by EDA toolkits, determining their proper configuration is a complex and very time-consuming DSE problem rarely addressed from a PPAD perspective. On one hand, the spatial and temporal complexity of considered targets and the level of abstraction of their descriptions pose problems for the rapid execution of fault injection campaigns. On the other hand, the multi-level nature of parameters offered by EDA toolkits lead to an explosion of possible configurations to exercise during experimentation. This paper shows how to combine the D-optimal design of experiments with FPGA-based and statistical fault injection to significantly reduce not only the number of such configurations but also the number of faults to inject and the time required to perform each injection. All of this without compromising the statistical significance of results. The proposal is exemplified through the  Xilinx Vivado Design Suite, which integrates one of the FPGA-based EDA toolkits most widely-used today in the industry, and the MC8051 IP core, a synthesizable microcontroller from Oregano Systems.