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Paper published at ITACA-WIICT 2018 (III)

The paper entitled: “Towards dependability-aware design space exploration using genetic algorithms”, written by Quentin Fabry, Ilya Tuzov, Juan-Carlos Ruiz and David de Andres is availabe at ITACA-WIICT 2018 poceedings.


The development of complex digital systems poses some design optimization problems that are today automatically addressed by Electronic Design Automation (EDA) tools. Deducing optimal configurations for EDA tools attending to specific implementation goals is challenging even for simple HW models. In deed, previous research demonstrates that such configurations may have a non-negligible impact on the performance, power-consumption, occupied area and dependability (PPAD) features exhibited by resulting HW implementations. This paper proposes a genetic algorithm to cope with the selection of appropriate configurations of EDA tools. Regardless statistical approaches, this type of algorithms has the benefit of considering all the effects among all configuration flags and their iterations. Consequently, they have a great potential for finding out tool configurations leading to implementations exhibiting optimal PPAD scores. However, it also exists the risk of incurring in very time-consuming design space explorations, which may limit the usability of the approach in practice. Since the behavior of the genetic algorithm will be strongly conditioned by the initially selected population and the mutation, crossover and filtering functions that will be selected for promoting evolution, these parameters must be determined very carefully on a case per case basis. In this publication, we will rely on a multilinear regression model estimating the impact of synthesis flags on the PPAD features exhibited by the implementation of an Intel 8051 microcontroller model. Beyond reported results, this preliminar research show how and to what extend genetic algorithms can be integrated and use in the semi-custom design flow followed today by major HW manufacturers.

Paper published at ITACA-WIICT 2018 (II)

The paper entitled: “Energy-aware Design Space Exploration for Optimal Implementation Parameters Tuning”, written by Ilya Tuzov, David de Andrés, and Juan Carlos Ruiz is availabe at ITACA-WIICT 2018 poceedings.


Determining the optimum configuration of semicustom implementation tools to simultaneously optimize the energy consumption, maximum clock frequency, and area of the target circuit requires navigating
through millions of configurations. Existing design space exploration approaches, like genetic algorithms, try to reduce as much as possible the number of configurations that must be implemented to find the (close to) optimum configuration. However, these approaches are not suitable when dependability-related properties must be also taken into account.
To accurately estimate these properties, extensive simulation-based fault injection experiments must be executed for each configuration, leading to unfeasible experimentation times. This work proposes an alternative approach, based on statistical and operational research artifacts, to drastically reduce the design space while preserving the accuracy of results, thus, enabling the energy-aware design space exploration for semicustom implementation of logic circuits.

Paper published at ITACA-WIICT 2018 (I)

The paper entitled: “A comparison of two different matrix Error Correction Codes”, written by J. Gracia-Morán, L.J. Saiz-Adalid, D. Gil-Tomás and P.J. Gil-Vicente is availabe at ITACA-WIICT 2018 poceedings.


Due to the continuous increment in the integration scale, the faultrate in computer memory systems has augmented. Thus, the probability of oc-currence of Single Cell Upsets(SCUs) or Multiple Cell Upsets(MCUs) also in-creases. A common solution is the use of Error Correction Codes (ECCs). However, when using ECCs, a good balance between the error coverage, the redundancy introduced and the area, power and delay overheadsof the encoders and decoders circuits must be achieved. In this sense, there exist different proposals to tolerate MCUs. For example, matrix codes are codes able to detect and/or correct MCUs usinga two-dimensional format. However, these codes introduce a great redundancy, which leads to an excessive area, power and delay overhead.In this paper we present a complete comparison of two recently introduced ma-trix codes