On July, 18th, Juan Carlos Ruiz has participated in the Summer School CPS 2018. His talk was titled “Design and Verification of Safe and Secure VLSI Systems”.
Current embedded VLSI systems are widespread and operate in multitude of applications in different markets, ranging from life support, industrial control, or avionics to consumer electronics. It is unquestionable that critical systems require different degrees of fault tolerance and security, given the human lives or great investments at stake, but nowadays the lack of robustness exhibited by consumer products (against unexpected failures and attacks) can also undermine their success in the marketplace and negatively affect the reputation of the manufacturer.
On the one hand, current practices for the design and deployment of hardware fault and intrusion-tolerance techniques remain in practice specific (defined on a case-per-case basis) and mostly manual and error prone. This situation is aggravated by considerations relating to time-to-market costs that promote the reuse and integration of (black- and white-box) IP cores developed by third and sometimes untrusted parties. This seminar addresses the challenging problems of engineering HW fault tolerance strategies in a generic way and supporting their subsequent instantiation. This approach relies on metaprogramming to specify fault tolerance mechanisms and open compilation to automate their deployment on target cores.
On the other hand, the assessment, verification, optimization and selection (benchmarking) of resulting HW implementations is far from being properly supported by existing Electronic Design Automation (EDA) tools when dependability becomes an important design concern. This seminar will address this situation with efficiency and flexibility in mind. It will be explained how, and to what extent, the HW implementation and analysis phases can be customized while relying on existing off-the-self languages, synthesis, mapping, placement and routing tools and technology-dependent libraries. Three different embedded processor models will be used to exemplify how the aforementioned challenges can be addressed in practice when considering FPGAs as final implementation devices.
Presentation slides are accesible using this link: 07.2018.ET.INSA-Toulouse.Final.UPV
The paper entitled “Towards dependability-aware design space exploration using genetic algorithms” written by Quentin Fabry, Ilya Tuzov, Juan-Carlos Ruiz and David de Andrés has been accepted in the Workshop on Innovation on Information and Communication Technologies (ITACA-WIICT 2018)
The development of complex digital systems poses some design optimization problems that are today automatically addressed by Electronic Design Automation (EDA) tools. Deducing optimal configurations for EDA tools attending to specific implementation goals is challenging even for simple HW models. In deed, previous research demonstrates that such configurations may have a non-negligible impact on the performance, power-consumption, occupied area and dependability (PPAD) features exhibited by resulting HW implementations. This paper proposes a genetic algorithm to cope with the selection of appropriate configurations of EDA tools. Regardless statistical approaches, this type of algorithms has the benefit of considering all the effects among all configuration flags and their iterations. Consequently, they have a great potential for finding out tool configurations leading to implementations exhibiting optimal PPAD scores. However, it also exists the risk of incurring in very time-consuming design space explorations, which may limit the usability of the approach in practice. Since the behavior of the genetic algorithm will be strongly conditioned by the initially selected population and the mutation, crossover and filtering functions that will be selected for promoting evolution, these parameters must be determined very carefully on a case per case basis. In this publication, we will rely on a multilinear regression model estimating the impact of synthesis flags on the PPAD features exhibited by the implementation of an Intel 8051 microcontroller model. Beyond reported results, this preliminar research show how and to what extend genetic algorithms can be integrated and use in the semi-custom design flow followed today by major HW manufacturers.
The paper entitled “Energy-aware Design Space Exploration for Optimal Implementation Parameters Tuning” written by Ilya Tuzov, David de Andrés and Juan Carlos Ruiz has been accepted in the Workshop on Innovation on Information and Communication Technologies (ITACA-WIICT 2018)
Determining the optimum configuration of semicustom implementation tools to simultaneously optimize the energy consumption, maximum clock frequency, and area of the target circuit requires navigating through millions of configurations. Existing design space exploration approaches, like genetic algorithms, try to reduce as much as possible the number of configurations that must be implemented to find the (close to) optimum configuration. However, these approaches are not suitable when dependability-related properties must be also taken into account. To accurately estimate these properties, extensive simulation-based fault injection experiments must be executed for each configuration, leading to unfeasible experimentation times. This work proposes an alternative approach, based on statistical and operational research artifacts, to drastically reduce the design space while preserving the accuracy of results, thus, enabling the energy-aware design space exploration for semicustom implementation of logic circuits.
The paper entitled “A comparison of two different matrix Error Correction Codes” written by J. Gracia-Morán, L.J. Saiz-Adalid, D. Gil-Tomás and P.J. Gil-Vicente has been accepted in the Workshop on Innovation on Information and Communication Technologies (ITACA-WIICT 2018)
Due to the continuous increment in the integration scale, the fault rate in computer memory systems has augmented. Thus, the probability of occurrence of Single Cell Upsets (SCUs) or Multiple Cell Upsets (MCUs) also increases. A common solution is the use of Error Correction Codes (ECCs). However, when using ECCs, a good balance between the error coverage, the redundancy introduced, and the area, power and delay overheads of the encoders and decoders circuits must be achieved.
In this sense, there exist different proposals to tolerate MCUs. For example, matrix codes are codes able to detect and/or correct MCUs using a two-dimensional format. However, these codes introduce a great redundancy, which leads to an excessive area, power and delay overhead.
In this paper we present a complete comparison of two recently introduced matrix codes.