Category Archives: Workshop

Last 18 September, J. Gracia-Morán presented the paper entitled “Mejora de un Código de Corrección de Errores para tolerar fallos adyacentes bidimensionales” at the Jornadas SARTECO 2019.

The paper entitled “Mejora de un Código de Corrección de Errores para tolerar fallos adyacentes bidimensionales” written by J. Gracia-Morán, L.J. Saiz-Adalid, D. Gil-Tomás, J.C. Baraza-Calvo and P.J. Gil-Vicente has been accepted at Jornadas SARTECO 2019.

Abstract:

Durante estos últimos años, el desarrollo tecnológico ha permitido aumentar la escala de integración de los circuitos integrados. En particular, este aumento ha posibilitado la creación de sistemas de memoria de gran capacidad. Sin embargo, también ha provocado un incremento en su tasa de fallos, aumentando la probabilidad de que se produzcan Single Cell Upsets (SCUs) o Multiple Cell Upsets (MCUs).
Una posible solución para tolerar estos errores es el uso de Códigos de Corrección de Errores (del inglés Error Correction Codes – ECCs). Dependiendo del ECC introducido, es posible corregir una gran variedad de tipos de errores, teniendo en cuenta que la introducción de un ECC implica una serie de sobrecargas a considerar, sobre todo cuando el ECC se utiliza en aplicaciones empotradas.
En un trabajo anterior presentamos un ECC diseñado para corregir fallos adyacentes, apto para aplicaciones empotradas. En este trabajo se presenta una mejora de este ECC que amplía la cobertura de error frente a fallos adyacentes sin aumentar el número de bits extra necesarios para corregirlos.

The paper entitled “Comparison of an Improved Matrix-based Error Correction Code”, written by J. Gracia-Morán, L.J. Saiz-Adalid, D. Gil-Tomás, J.C. Baraza-Calvo and P.J. Gil-Vicente has been accepted in the Workshop on Innovation on Information and Communication Technologies (ITACA-WIICT 2019).

Abstract:

Nowadays, the probability of occurrence of Single Cell Upsets (SCUs) or Multiple Cell Upsets (MCUs) has increased due to the continuous in-crement in the integration scale of CMOS technology, that has provoked an augment in the fault rate. SCUs and MCUs are particularly common in comput-er memory systems. To tolerate errors, it is common the use of Error Correction Codes (ECCs). Nevertheless, when using ECCs, a series of overheads are add-ed: extra bits to detect and/or correct errors, and some area, power consumption and delay overheads of the encoders and decoders circuits.
In order to tolerate MCUs, different approaches have been presented in the lit-erature. Specifically, in this work, we present a complete comparison of differ-ent matrix-based ECCs, some of them recently presented.

The paper entitled: “Towards dependability-aware design space exploration using genetic algorithms”, written by Quentin Fabry, Ilya Tuzov, Juan-Carlos Ruiz and David de Andres is availabe at ITACA-WIICT 2018 poceedings.

Abstract:

The development of complex digital systems poses some design optimization problems that are today automatically addressed by Electronic Design Automation (EDA) tools. Deducing optimal configurations for EDA tools attending to specific implementation goals is challenging even for simple HW models. In deed, previous research demonstrates that such configurations may have a non-negligible impact on the performance, power-consumption, occupied area and dependability (PPAD) features exhibited by resulting HW implementations. This paper proposes a genetic algorithm to cope with the selection of appropriate configurations of EDA tools. Regardless statistical approaches, this type of algorithms has the benefit of considering all the effects among all configuration flags and their iterations. Consequently, they have a great potential for finding out tool configurations leading to implementations exhibiting optimal PPAD scores. However, it also exists the risk of incurring in very time-consuming design space explorations, which may limit the usability of the approach in practice. Since the behavior of the genetic algorithm will be strongly conditioned by the initially selected population and the mutation, crossover and filtering functions that will be selected for promoting evolution, these parameters must be determined very carefully on a case per case basis. In this publication, we will rely on a multilinear regression model estimating the impact of synthesis flags on the PPAD features exhibited by the implementation of an Intel 8051 microcontroller model. Beyond reported results, this preliminar research show how and to what extend genetic algorithms can be integrated and use in the semi-custom design flow followed today by major HW manufacturers.

The paper entitled: “Energy-aware Design Space Exploration for Optimal Implementation Parameters Tuning”, written by Ilya Tuzov, David de Andrés, and Juan Carlos Ruiz is availabe at ITACA-WIICT 2018 poceedings.

Abstract:

Determining the optimum configuration of semicustom implementation tools to simultaneously optimize the energy consumption, maximum clock frequency, and area of the target circuit requires navigating
through millions of configurations. Existing design space exploration approaches, like genetic algorithms, try to reduce as much as possible the number of configurations that must be implemented to find the (close to) optimum configuration. However, these approaches are not suitable when dependability-related properties must be also taken into account.
To accurately estimate these properties, extensive simulation-based fault injection experiments must be executed for each configuration, leading to unfeasible experimentation times. This work proposes an alternative approach, based on statistical and operational research artifacts, to drastically reduce the design space while preserving the accuracy of results, thus, enabling the energy-aware design space exploration for semicustom implementation of logic circuits.

The paper entitled: “A comparison of two different matrix Error Correction Codes”, written by J. Gracia-Morán, L.J. Saiz-Adalid, D. Gil-Tomás and P.J. Gil-Vicente is availabe at ITACA-WIICT 2018 poceedings.

Abstract:

Due to the continuous increment in the integration scale, the faultrate in computer memory systems has augmented. Thus, the probability of oc-currence of Single Cell Upsets(SCUs) or Multiple Cell Upsets(MCUs) also in-creases. A common solution is the use of Error Correction Codes (ECCs). However, when using ECCs, a good balance between the error coverage, the redundancy introduced and the area, power and delay overheadsof the encoders and decoders circuits must be achieved. In this sense, there exist different proposals to tolerate MCUs. For example, matrix codes are codes able to detect and/or correct MCUs usinga two-dimensional format. However, these codes introduce a great redundancy, which leads to an excessive area, power and delay overhead.In this paper we present a complete comparison of two recently introduced ma-trix codes

J. Gracia-Morán has presented the paper entitled “Un nuevo Código de Corrección de Errores matricial con baja redundancia“, presented at the Jornadas Sarteco, held in Teruel, 12-14 September, 2018.

The paper entitled “Towards dependability-aware design space exploration using genetic algorithms” written by Quentin Fabry, Ilya Tuzov, Juan-Carlos Ruiz and David de Andrés has been accepted in the Workshop on Innovation on Information and Communication Technologies (ITACA-WIICT 2018)

Abstract:

The development of complex digital systems poses some design optimization problems that are today automatically addressed by Electronic Design Automation (EDA) tools. Deducing optimal configurations for EDA tools attending to specific implementation goals is challenging even for simple HW models. In deed, previous research demonstrates that such configurations may have a non-negligible impact on the performance, power-consumption, occupied area and dependability (PPAD) features exhibited by resulting HW implementations. This paper proposes a genetic algorithm to cope with the selection of appropriate configurations of EDA tools. Regardless statistical approaches, this type of algorithms has the benefit of considering all the effects among all configuration flags and their iterations. Consequently, they have a great potential for finding out tool configurations leading to implementations exhibiting optimal PPAD scores. However, it also exists the risk of incurring in very time-consuming design space explorations, which may limit the usability of the approach in practice. Since the behavior of the genetic algorithm will be strongly conditioned by the initially selected population and the mutation, crossover and filtering functions that will be selected for promoting evolution, these parameters must be determined very carefully on a case per case basis. In this publication, we will rely on a multilinear regression model estimating the impact of synthesis flags on the PPAD features exhibited by the implementation of an Intel 8051 microcontroller model. Beyond reported results, this preliminar research show how and to what extend genetic algorithms can be integrated and use in the semi-custom design flow followed today by major HW manufacturers.

The paper entitled “Energy-aware Design Space Exploration for Optimal Implementation Parameters Tuning” written by Ilya Tuzov, David de Andrés and Juan Carlos Ruiz has been accepted in the Workshop on Innovation on Information and Communication Technologies (ITACA-WIICT 2018)

Abstract:

Determining the optimum configuration of semicustom implementation tools to simultaneously optimize the energy consumption, maximum clock frequency, and area of the target circuit requires navigating through millions of configurations. Existing design space exploration approaches, like genetic algorithms, try to reduce as much as possible the number of configurations that must be implemented to find the (close to) optimum configuration. However, these approaches are not suitable when dependability-related properties must be also taken into account. To accurately estimate these properties, extensive simulation-based fault injection experiments must be executed for each configuration, leading to unfeasible experimentation times. This work proposes an alternative approach, based on statistical and operational research artifacts, to drastically reduce the design space while preserving the accuracy of results, thus, enabling the energy-aware design space exploration for semicustom implementation of logic circuits.