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PhD Sobresaliente Cum Laude

The PhD work entitled ““Improving the process of analysis and comparison of results in dependability benchmarking for computer systems”, developed by Miquel Martínez Raga, and directed by David de Andres and Juan Carlos Ruiz has been awarded with a claification of Sobresaliente Cum Laude.


PhD Defense

Our PhD student, Miquel Martínez Raga, has succesfully defended his thesis entitled “Improving the process of analysis and comparison of results in dependability benchmarking for computer systems”.


Seminar INSA Ecole Été 2018 in CyberPhysical Systems

On July, 18th, Juan Carlos Ruiz has participated in the Summer School CPS 2018. His talk was titled “Design and Verification of Safe and Secure VLSI Systems”.


Current embedded VLSI systems are widespread and operate in multitude of applications in different markets, ranging from life support, industrial control, or avionics to consumer electronics. It is unquestionable that critical systems require different degrees of fault tolerance and security, given the human lives or great investments at stake, but nowadays the lack of robustness exhibited by consumer products (against unexpected failures and attacks) can also undermine their success in the marketplace and negatively affect the reputation of the manufacturer.

On the one hand, current practices for the design and deployment of hardware fault and intrusion-tolerance techniques remain in practice specific (defined on a case-per-case basis) and mostly manual and error prone. This situation is aggravated by considerations relating to time-to-market costs that promote the reuse and integration of (black- and white-box) IP cores developed by third and sometimes untrusted parties. This seminar addresses the challenging problems of engineering HW fault tolerance strategies in a generic way and supporting their subsequent instantiation. This approach relies on metaprogramming to specify fault tolerance mechanisms and open compilation to automate their deployment on target cores.

On the other hand, the assessment, verification, optimization and selection (benchmarking) of resulting HW implementations is far from being properly supported by existing Electronic Design Automation (EDA) tools when dependability becomes an important design concern. This seminar will address this situation with efficiency and flexibility in mind. It will be explained how, and to what extent, the HW implementation and analysis phases can be customized while relying on existing off-the-self languages, synthesis, mapping, placement and routing tools and technology-dependent libraries. Three different embedded processor models will be used to exemplify how the aforementioned challenges can be addressed in practice when considering FPGAs as final implementation devices.

Presentation slides are accesible using this link: 07.2018.ET.INSA-Toulouse.Final.UPV

Seminar: “FPGA-based fault injection”

Next Thursday 31/05/2018 at 12h30, researcher Jose Luis Nunes (University of Coimbra) will provide a talk describing his research on FPGA-based Fault Injection. Find here after the information concerning this seminar:
Title: FPGA-based Fault Injection
Summary: Reconfigurable embedded devices built on SRAM-based Field Programmable Gate Arrays (FPGA) are being increasingly used in critical embedded applications. Its susceptibility to Single Event Upsets (SEU) requires the use of fault tolerant designs, for which fault injection is one of the most accepted verification techniques.
In this talk implementation details of FIRED, a fault injector targeted at SRAM-based FPGAs (Virtex-5) for dependability evaluation of critical systems are presented. This tool is able to perform hardware fault injection in real-time, by inserting bitflips at the SRAM cells through Partial Dynamic Reconfiguration (PDR).
The architecture of an updated version of the tool, targetting current state-of-the-art devices (Xilinx 7-series) is also discussed. This new tool will take advantage of Soft Error Mitigation (SEM) core to support the fault injection.
CV of the speaker: José Luís Nunes is a professor at Coimbra Polytechnic where he teaches Operating Systems, Digital Systems and Computer Architectures. He is a member of the Software and Systems Engineering (SSE) research team at Center for Informatics and Systems of the University of Coimbra (CISUC), enrolled in the PhD program. His current research topics include dependability, fault injection, FPGAs and real-time embedded system.

Seminar at LAAS

This week, Juan Carlos Ruiz has been teaching the entitled seminar “Statistical Fault Injection: When is it enough in robustness assessment?

Simulation-based fault injection is commonly used to assess the robustness of hardware components modelled using Hardware Description Languages (HDL). The current complexity of modern circuits usually makes not feasible the consideration during experimentation of all possible combinations of fault models, targets, and times. By assuming a confidence interval and error margin, statistical fault injection exploits the principle of statistical sampling to reduce the number of experiments while keeping the results representative of the whole population of fault injections. Since the percentage of injected faults leading to failure is a priori unknown, such number of experiments is usually determined by selecting the value maximizing the sample size. This presentation argues that this conservative assumption leads to a worst-case scenario that can be improved. It proposes an new iterative approach to progressively adjust the number of experiments by estimating the percentage of those leading to failure and the error of such estimation. This proposal provides new means to decide when to stop a fault injection campaign and to estimate the error existing in the results finally reported.