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Panel at CARS 2019

Last September, 17th, Juan Carlos Ruiz took part in the panel “Autonomous driving: safety and security issues”, celebrated in the 5th International Workshop on Critical Automotive Applications: Robustness & Safety (CARS 2019), collocated with EDCC 2019 in Naples, Italy.

Presentation at EDCC 2019

Juan Carlos Ruiz has presented the paper entitled Robustness-aware design space exploration by iteratively augmenting and repairing D-optimal designs”, written by Ilya Tuzov, David De Andrés and Juan Carlos Ruiz.

Abstract:

Design space exploration (DSE) is nowadays of utmost importance to implement HW designs with acceptable levels of performance, power consumption, area and dependability (PPAD). Electronic Design Automation (EDA) tools support the transformation of HW description models into technology-dependent implementations. Although designers can influence this process by tuning the parameters offered by EDA toolkits, determining their proper configuration is a complex and very time-consuming DSE problem rarely addressed from a PPAD perspective. On one hand, the spatial and temporal complexity of considered targets and the level of abstraction of their descriptions pose problems for the rapid execution of fault injection campaigns. On the other hand, the multi-level nature of parameters offered by EDA toolkits lead to an explosion of possible configurations to exercise during experimentation. This paper shows how to combine the D-optimal design of experiments with FPGA-based and statistical fault injection to significantly reduce not only the number of such configurations but also the number of faults to inject and the time required to perform each injection. All of this without compromising the statistical significance of results. The proposal is exemplified through the Xilinx Vivado Design Suite, which integrates one of the FPGA-based EDA toolkits most widely-used today in the industry, and the MC8051 IP core, a synthesizable microcontroller from Oregano Systems.

DSN 2020 will be held at UPV

The Fault Tolerant Systems Group (STF) of the Institute ITACA from the UPV will host the next International Conference on Dependable Systems and Networks (DSN), that will be held in Valencia in June 2020.

Over the years, the International Conference on Dependable Systems and Networks has pioneered the fusion between dependability and security research, understanding the need to simultaneously fight against accidental faults, intentional cyber-attacks, design errors, and unexpected operating conditions. These concerns can no longer be tackled in isolation, neither in general IT nor in internet-of-things, cyber-physical systems, autonomous transportation, robotics and application areas.

We hope to see you in Valencia!!

Paper accepted at EDCC 2019

The paper entitled “Robustness-aware design space exploration through iterative refinement of D-optimal designs”, written by Ilya Tuzov, David de Andrés and Juan-Carlos Ruiz has been accepted at EDCC 2019.

Abstract:

Design space exploration (DSE) is nowadays of utmost importance to implement HW designs with acceptable levels of performance, power consumption, area and dependability (PPAD).  Electronic Design Automation (EDA) tools support the transformation of HW description models into technology-dependent implementations. Although designers can influence this process by tuning the parameters offered by EDA toolkits, determining their proper configuration is a complex and very time-consuming DSE problem rarely addressed from a PPAD perspective. On one hand, the spatial and temporal complexity of considered targets and the level of abstraction of their descriptions pose problems for the rapid execution of fault injection campaigns. On the other hand, the multi-level nature of parameters offered by EDA toolkits lead to an explosion of possible configurations to exercise during experimentation. This paper shows how to combine the D-optimal design of experiments with FPGA-based and statistical fault injection to significantly reduce not only the number of such configurations but also the number of faults to inject and the time required to perform each injection. All of this without compromising the statistical significance of results. The proposal is exemplified through the  Xilinx Vivado Design Suite, which integrates one of the FPGA-based EDA toolkits most widely-used today in the industry, and the MC8051 IP core, a synthesizable microcontroller from Oregano Systems.

Happy New Year 2019!

The DINAMOS Team wants to wish you a happy new year 2019.

LADC 2018 Best Paper Award

The paper entitled “Speeding-up robustness assessment of HDL models through profiling and multi-level fault injection”, written Ilya Tuzov, David de Andres and Juan Carlos Ruiz has been awarded as Best Paper in LADC 2018.

Congratulations!!

LADC 2018 Presentation (II)

Luis J. Saiz has presented at LADC 2018 the paper entitled “Correction of Adjacent Errors with Low Redundant Matrix Error Correction Codes” written by Joaquin Gracia-Moran, Luis-J. Saiz-Adalid, Juan-Carlos Baraza-Calvo and Pedro Gil-Vicente.

LADC 2018 Presentation (I)

Juan Carlos Ruiz has presented at LADC 2018 the best paper candidate entitled “Speeding-up robustness assessment of HDL models through profiling and multi-level fault injection”, written Ilya Tuzov, David de Andres and Juan Carlos Ruiz.

Presentation at EDCC 2018

David de Andrés has presented the paper entitled “Accurate Robustness Assessment of HDL Models through Iterative Statistical Fault Injection” at EDCC 2018.

This work has been selected as one of the “Distinguished Papers”.

Congratulations!!

Best paper award nomination at LADC

The paper entitled “ Speeding-up robustness assessment of HDL models through profiling and multi-level fault injection”, authored by Ilya Tuzov, David de Andrés and Juan-Carlos Ruiz, has been nominated to best paper at LADC 2018.

Congratulations!!!