Category Archives: Paper

Juan Carlos Ruiz has presented the paper entitled “Robustness-aware design space exploration by iteratively augmenting and repairing D-optimal designs”, written by Ilya Tuzov, David De Andrés and Juan Carlos Ruiz.

Abstract:

Design space exploration (DSE) is nowadays of utmost importance to implement HW designs with acceptable levels of performance, power consumption, area and dependability (PPAD). Electronic Design Automation (EDA) tools support the transformation of HW description models into technology-dependent implementations. Although designers can influence this process by tuning the parameters offered by EDA toolkits, determining their proper configuration is a complex and very time-consuming DSE problem rarely addressed from a PPAD perspective. On one hand, the spatial and temporal complexity of considered targets and the level of abstraction of their descriptions pose problems for the rapid execution of fault injection campaigns. On the other hand, the multi-level nature of parameters offered by EDA toolkits lead to an explosion of possible configurations to exercise during experimentation. This paper shows how to combine the D-optimal design of experiments with FPGA-based and statistical fault injection to significantly reduce not only the number of such configurations but also the number of faults to inject and the time required to perform each injection. All of this without compromising the statistical significance of results. The proposal is exemplified through the Xilinx Vivado Design Suite, which integrates one of the FPGA-based EDA toolkits most widely-used today in the industry, and the MC8051 IP core, a synthesizable microcontroller from Oregano Systems.

The paper entitled “Robustness-aware design space exploration through iterative refinement of D-optimal designs”, written by Ilya Tuzov, David de Andrés and Juan-Carlos Ruiz has been accepted at EDCC 2019.

Abstract:

Design space exploration (DSE) is nowadays of utmost importance to implement HW designs with acceptable levels of performance, power consumption, area and dependability (PPAD).  Electronic Design Automation (EDA) tools support the transformation of HW description models into technology-dependent implementations. Although designers can influence this process by tuning the parameters offered by EDA toolkits, determining their proper configuration is a complex and very time-consuming DSE problem rarely addressed from a PPAD perspective. On one hand, the spatial and temporal complexity of considered targets and the level of abstraction of their descriptions pose problems for the rapid execution of fault injection campaigns. On the other hand, the multi-level nature of parameters offered by EDA toolkits lead to an explosion of possible configurations to exercise during experimentation. This paper shows how to combine the D-optimal design of experiments with FPGA-based and statistical fault injection to significantly reduce not only the number of such configurations but also the number of faults to inject and the time required to perform each injection. All of this without compromising the statistical significance of results. The proposal is exemplified through the  Xilinx Vivado Design Suite, which integrates one of the FPGA-based EDA toolkits most widely-used today in the industry, and the MC8051 IP core, a synthesizable microcontroller from Oregano Systems.

The paper entitled “Speeding-up robustness assessment of HDL models through profiling and multi-level fault injection”, written Ilya Tuzov, David de Andres and Juan Carlos Ruiz has been awarded as Best Paper in LADC 2018.

Congratulations!!

Luis J. Saiz has presented at LADC 2018 the paper entitled “Correction of Adjacent Errors with Low Redundant Matrix Error Correction Codes” written by Joaquin Gracia-Moran, Luis-J. Saiz-Adalid, Juan-Carlos Baraza-Calvo and Pedro Gil-Vicente.

Juan Carlos Ruiz has presented at LADC 2018 the best paper candidate entitled “Speeding-up robustness assessment of HDL models through profiling and multi-level fault injection”, written Ilya Tuzov, David de Andres and Juan Carlos Ruiz.

David de Andrés has presented the paper entitled “Accurate Robustness Assessment of HDL Models through Iterative Statistical Fault Injection” at EDCC 2018.

This work has been selected as one of the “Distinguished Papers”.

Congratulations!!

The paper entitled “ Speeding-up robustness assessment of HDL models through profiling and multi-level fault injection”, authored by Ilya Tuzov, David de Andrés and Juan-Carlos Ruiz, has been nominated to best paper at LADC 2018.

Congratulations!!!

The paper entitled “ Speeding-up robustness assessment of HDL models through profiling and multi-level fault injection”, authored by Ilya Tuzov, David de Andrés and Juan-Carlos Ruiz, has been accepted at LADC 2018.

Abstract:

Simulation-based fault injection is an indispensable technique to assess the robustness of hardware components defined by means of hardware description languages (HDL). However, the high complexity of modern hardware and its strict verification accuracy requirements lead to an unfeasible number of fault injection experiments, even when following statistical (instead of exhaustive) approaches, as accurate implementation-level models are up to three orders of magnitude slower than (inaccurate) behavioural ones. This paper proposes the combined use of multi-level fault injection in sequential logic and the profiling of the use of combinational logic to guarantee results’ accuracy while keeping experimentation duration within reasonable time-bounds. First, the sequential logic generated at the implementation-level model is matched with associated structures at its related behavioural-level model. In such a way, most fault injection experiments targeting sequential logic could be executed at the much faster behavioural level, while maintaining the accuracy of results. Second, by profiling the implementation-level model, run-time statistics (inactive macrocells, switching activity, etc.) can be exploited to keep result precision while reducing the number of experiments targeting combinational logic. The case study of three embedded processor models illustrates both approaches and quantifies the experimental speed-up derived from their combined use.

The paper entitled “Correction of Adjacent Errors with Low Redundant Matrix Error Correction Codes”, authored by J. Gracia-Moran, L.J. Saiz-Adalid, J.C. Baraza-Calvo and P.J. Gil-Vicente, has been accepted at LADC 2018.

Abstract:

The continuous growth of the integration scale in CMOS circuits has derived in an increase in the memory systems capacity, but also in their fault rate. In this way, the probabilities of suffering Single Cell Upsets (SCUs) or Multiple Cell Upsets (MCUs) has thus raised.
Traditionally, Error Correction Codes (ECCs) are used in memory systems to correct errors. However, when using ECCs, it is necessary to find a good balance between the redundancy of the code; the area, power consumption and delay overheads of the encoding and decoding circuits; and the error coverage achieved.
In this work, we present two new low-redundant matrix ECCs that are able to correct different types of adjacent errors. Both codes have the same error coverage, but different levels of redundancy. In this way, we have been able to study the influence of these different levels of low redundancy in the area, power consumption and delay overheads. We have also compared our proposals to a well-known matrix code, in terms of overhead vs. coverage using a recently introduced metric. In all cases, our proposals get better scores.

Our PhD student, Ilya Tuzov, has presented the work “DAVOS: EDA toolkit for dependability assessment, verification, optimisation and selection of hardware models” at DSN 2018, that is being celebrating in Luxembourg.