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Monthly Archives: June 2018

Visit from Nepal

27 June, 2018

Professor Dr. Dinesh Kumar Sharma, Professor Dr. Subarna Shakya and Professor Dr. Tri Ratna Bajracharya from the Tribhuvan University in Nepal has visited us today.

 

Presentation at DSN 2018

27 June, 2018

Our PhD student, Ilya Tuzov, has presented the work “DAVOS: EDA toolkit for dependability assessment, verification, optimisation and selection of hardware models” at DSN 2018, that is being celebrating in Luxembourg.

 

Paper accepted at Jornadas SARTECO 2018

26 June, 2018

The paper entitled “Un nuevo Código de Corrección de Errores matricial con baja redundancia” written by J. Gracia-Morán, L.J. Saiz-Adalid, D. Gil-Tomás and P.J. Gil-Vicente has been accepted in the Jornadas SARTECO 2018.

The abstract of this work says:

Actualmente, y debido al continuo aumento en la escala de integración, la tasa de fallos en los sistemas de memoria de los computadores ha aumentado. Así, la probabilidad de que se produzcan Single Cell Upsets (SCUs) o Multiple Cell Upsets (MCUs) aumenta. Una solución común es el uso de Códigos de Corrección de Errores (ECCs). Sin embargo, cuando se utilizan ECCs en aplicaciones empotradas, se debe lograr un buen equilibrio entre la cobertura de errores, la redundancia introducida y la eficiencia en términos de área de silicio ocupada, potencia consumida y retardo de los circuitos de codificación y decodificación.
En este sentido, existen diferentes propuestas para tolerar MCUs. Por ejemplo, los códigos matriciales utilizan códigos de Hamming y controles de paridad en un formato bidimensional para detectar y/o corregir MCUs. Sin embargo, estos códigos introducen una gran redundancia, lo que conlleva una sobrecarga excesiva con respecto al área, potencia consumida y retardo.
En este trabajo presentamos un nuevo código matricial con una baja redundancia, que permite corregir diferentes patrones de MCUs y que no introduce una gran sobrecarga en los circuitos de codificación y decodificación.

Paper accepted at IEEE Transactions on VLSI

1 June, 2018

The paper entitled “Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications”, written by Joaquín Gracia-Morán, Luis J. Saiz-Adalid, Daniel Gil-Tomás, and Pedro J. Gil-Vicente has been accepted at the IEEE Transactions on VLSI.

Abstract:
Currently, faults suffered by SRAM memory systems have increased due to the aggressive CMOS integration density. Thus, the probability of occurrence of single-cell upsets (SCUs) or multiple-cell upsets (MCUs) augments. One of the main causes of MCUs in space applications is cosmic radiation. A common solution is the use of error correction codes (ECCs). Nevertheless, when using ECCs in space applications, they must achieve a good balance between error coverage and redundancy, and their encoding/decoding circuits must be efficient in terms of area, power, and delay. Different codes have been proposed to tolerate MCUs. For instance, Matrix codes use Hamming codes and parity checks in a bi-dimensional layout to correct and detect some patterns of MCUs. Recently presented, column–line–code (CLC) has been designed to tolerate MCUs in space applications. CLC is a modified Matrix code, based
on extended Hamming codes and parity checks. Nevertheless, a common property of these codes is the high redundancy introduced. In this paper, we present a series of new low-redundant ECCs able to correct MCUs with reduced area, power, and delay overheads. Also, these new codes maintain, or even improve, memory error coverage with respect to Matrix and CLC codes.

More info at: https://ieeexplore.ieee.org/document/8370138/