The paper entitled “Simulating the effects of logic faults in implementation-level VITAL-compliant models” authored by Ilya Tuzov, David de Andrés and Juan Carlos Ruiz has been publised in Computing journal.
Cite as: I. Tuzov, D. de Andrés, J.-C. Ruiz, “Simulating the effects of logic faults in implementation-level VITAL-compliant models”, Computing, Vol. 101, No. 2, 2019, pp. 77–96, ISSN: 0010-485X, DOI: https://doi.org/10.1007/s00607-018-0651-4.
Simulation-based fault injection is a well-known technique to assess the dependability of hardware designs specified using hardware description languages (HDL). Although logic faults are usually introduced in models defined at the register transfer level (RTL), most accurate results can be obtained by considering implementation-level ones, which reflect the actual structure and timing of the circuit. These models consist of a list of interconnected technology-specific components (macrocells), provided by vendors and annotated with post-place-and-route delays. Macrocells described in the very high speed integrated circuit HDL (VHDL) should also comply with the VHDL initiative towards application specific integrated circuit libraries (VITAL) standard to be interoperable across standard simulators. However, the rigid architecture imposed by VITAL makes that fault injection procedures applied at RTL cannot be used straightforwardly. This work identifies a set of generic operations on VITAL-compliant macrocells that are later used to define how to accurately simulate the effects of common logic fault models. The generality of this proposal is supported by the definition of a platform-specific fault procedure based on these operations. Three embedded processors, implemented using the Xilinx’s toolchain and SIMPRIM library of macrocells, are considered as a case study, which exposes the gap existing between the robustness assessment at both RTL and implementation-level.