Visit from Nepal
Professor Dr. Dinesh Kumar Sharma, Professor Dr. Subarna Shakya and Professor Dr. Tri Ratna Bajracharya from the Tribhuvan University in Nepal has visited us today.
Presentation at DSN 2018
Our PhD student, Ilya Tuzov, has presented the work “DAVOS: EDA toolkit for dependability assessment, verification, optimisation and selection of hardware models” at DSN 2018, that is being celebrating in Luxembourg.
Paper accepted at Jornadas SARTECO 2018
The paper entitled “Un nuevo Código de Corrección de Errores matricial con baja redundancia” written by J. Gracia-Morán, L.J. Saiz-Adalid, D. Gil-Tomás and P.J. Gil-Vicente has been accepted in the Jornadas SARTECO 2018. The abstract of this work says: Actualmente, y debido al continuo aumento en la escala de integración, la tasa de fallos en [...]
Paper accepted at IEEE Transactions on VLSI
The paper entitled “Improving Error Correction Codes for Multiple-Cell Upsets in Space Applications”, written by Joaquín Gracia-Morán, Luis J. Saiz-Adalid, Daniel Gil-Tomás, and Pedro J. Gil-Vicente has been accepted at the IEEE Transactions on VLSI. Abstract: Currently, faults suffered by SRAM memory systems have increased due to the aggressive CMOS integration density. Thus, the probability [...]