Paper accepted at LADC (II)

The paper entitled “ Speeding-up robustness assessment of HDL models through profiling and multi-level fault injection”, authored by Ilya Tuzov, David de Andrés and Juan-Carlos Ruiz, has been accepted at LADC 2018.

Abstract:

Simulation-based fault injection is an indispensable technique to assess the robustness of hardware components defined by means of hardware description languages (HDL). However, the high complexity of modern hardware and its strict verification accuracy requirements lead to an unfeasible number of fault injection experiments, even when following statistical (instead of exhaustive) approaches, as accurate implementation-level models are up to three orders of magnitude slower than (inaccurate) behavioural ones. This paper proposes the combined use of multi-level fault injection in sequential logic and the profiling of the use of combinational logic to guarantee results’ accuracy while keeping experimentation duration within reasonable time-bounds. First, the sequential logic generated at the implementation-level model is matched with associated structures at its related behavioural-level model. In such a way, most fault injection experiments targeting sequential logic could be executed at the much faster behavioural level, while maintaining the accuracy of results. Second, by profiling the implementation-level model, run-time statistics (inactive macrocells, switching activity, etc.) can be exploited to keep result precision while reducing the number of experiments targeting combinational logic. The case study of three embedded processor models illustrates both approaches and quantifies the experimental speed-up derived from their combined use.