9th International Workshop on Safety and Security of Intelligent Vehicles
David de Andrés is part of the Programm Committee of the 9th International Workshop on Safety and Security of Intelligent Vehicles. This workshop, co-located with DSN 2023, will be celebrated in Porto (Portugal), June 26, 2023.
DEFADAS: the new research project of STF@UPV
DEFADAS (Dependable-enough FPGA-Accelerated DNNs for Automotive Systems), the new reresearch project of STF@UPV, has started.
Paper available
The paper entitled “Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM”, written by J.-Carlos Baraza-Calvo, Joaquín Gracia-Morán, Luis-J. Saiz-Adalid, Daniel Gil-Tomás y Pedro-J. Gil-Vicente is available at Electronics journal. Abstract: Due to transistor shrinking, intermittent faults are a major concern in current digital systems. This work presents an adaptive fault [...]
Paper accepted at IEEE Transactions on Dependable and Secure Computing
The paper entitled “A Multi-criteria Analysis of Benchmark Results With Expert Support for Security Tools” written by Miquel Martínez, Juan-Carlos Ruiz, Nuno Antunes, David de Andrés and Marco Vieira has been accepted at IEEE Transactions on Dependable and Secure Computing journal. Abstract. The benchmarking of security tools is endeavored to determine which tools are more [...]
Paper accepted at Electronics Journal
The paper entitled “Proposal of an Adaptive Fault Tolerance Mechanism to Tolerate Intermittent Faults in RAM”, written by J.-Carlos Baraza-Calvo, Joaquín Gracia-Morán, Luis-J. Saiz-Adalid, Daniel Gil-Tomás y Pedro-J. Gil-Vicente has been accepted at Electronics journal. Abstract: Due to transistor shrinking, intermittent faults are a major concern in current digital systems. This work presents an adaptive [...]
Paper accepted at Electronics journal
The paper entitled “Reducing the Overhead of BCH Codes: New Double Error Correction Codes”, authored by Luis-J. Saiz-Adalid, Joaquín Gracia-Morán, Daniel Gil-Tomás, J.-Carlos Baraza-Calvo and Pedro-J. Gil-Vicente has been published at Electronics journal. Abstract The Bose-Chaudhuri-Hocquenghem (BCH) codes are a well-known class of powerful error correction cyclic codes. BCH codes can correct multiple errors with [...]
DSN 2020 Conference Tracks
DSN 2020, organized by the Fault Tolerant Systems Group of the University Politècnica de València, is a multi-track conference seeking for contributions in different tracks. More info in this link. We hope to see you here!!
Paper available at IEEE Access
The paper entitled “Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection”, authored by Luis-J. Saiz-Adalid, Joaquín Gracia-Morán, Daniel Gil-Tomás, J.-Carlos Baraza-Calvo and Pedro-J. Gil-Vicente is available at IEEE Access.
Paper accepted at IEEE Access
The paper entitled “Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection”, authored by Luis-J. Saiz-Adalid, Joaquín Gracia-Morán, Daniel Gil-Tomás, J.-Carlos Baraza-Calvo and Pedro-J. Gil-Vicente has been accepted at IEEE Access. Abstract Reliable computer systems employ error control codes (ECCs) to protect information from errors. For example, memories are frequently protected using single [...]
Presentation at Jornadas SARTECO 2019
Last 18 September, J. Gracia-Morán presented the paper entitled “Mejora de un Código de Corrección de Errores para tolerar fallos adyacentes bidimensionales” at the Jornadas SARTECO 2019.