The paper entitled “A comparison of two different matrix Error Correction Codes” written by J. Gracia-Morán, L.J. Saiz-Adalid, D. Gil-Tomás and P.J. Gil-Vicente has been accepted in the Workshop on Innovation on Information and Communication Technologies (ITACA-WIICT 2018)
Due to the continuous increment in the integration scale, the fault rate in computer memory systems has augmented. Thus, the probability of occurrence of Single Cell Upsets (SCUs) or Multiple Cell Upsets (MCUs) also increases. A common solution is the use of Error Correction Codes (ECCs). However, when using ECCs, a good balance between the error coverage, the redundancy introduced, and the area, power and delay overheads of the encoders and decoders circuits must be achieved.
In this sense, there exist different proposals to tolerate MCUs. For example, matrix codes are codes able to detect and/or correct MCUs using a two-dimensional format. However, these codes introduce a great redundancy, which leads to an excessive area, power and delay overhead.
In this paper we present a complete comparison of two recently introduced matrix codes.