On July, 18th, Juan Carlos Ruiz has participated in the Summer School CPS 2018. His talk was titled “Design and Verification of Safe and Secure VLSI Systems”.
Current embedded VLSI systems are widespread and operate in multitude of applications in different markets, ranging from life support, industrial control, or avionics to consumer electronics. It is unquestionable that critical systems require different degrees of fault tolerance and security, given the human lives or great investments at stake, but nowadays the lack of robustness exhibited by consumer products (against unexpected failures and attacks) can also undermine their success in the marketplace and negatively affect the reputation of the manufacturer.
On the one hand, current practices for the design and deployment of hardware fault and intrusion-tolerance techniques remain in practice specific (defined on a case-per-case basis) and mostly manual and error prone. This situation is aggravated by considerations relating to time-to-market costs that promote the reuse and integration of (black- and white-box) IP cores developed by third and sometimes untrusted parties. This seminar addresses the challenging problems of engineering HW fault tolerance strategies in a generic way and supporting their subsequent instantiation. This approach relies on metaprogramming to specify fault tolerance mechanisms and open compilation to automate their deployment on target cores.
On the other hand, the assessment, verification, optimization and selection (benchmarking) of resulting HW implementations is far from being properly supported by existing Electronic Design Automation (EDA) tools when dependability becomes an important design concern. This seminar will address this situation with efficiency and flexibility in mind. It will be explained how, and to what extent, the HW implementation and analysis phases can be customized while relying on existing off-the-self languages, synthesis, mapping, placement and routing tools and technology-dependent libraries. Three different embedded processor models will be used to exemplify how the aforementioned challenges can be addressed in practice when considering FPGAs as final implementation devices.
Presentation slides are accesible using this link: 07.2018.ET.INSA-Toulouse.Final.UPV