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Archivos anuales: 2019
Paper accepted at IEEE Access
The paper entitled «Ultrafast Codes for Multiple Adjacent Error Correction and Double Error Detection», authored by Luis-J. Saiz-Adalid, Joaquín Gracia-Morán, Daniel Gil-Tomás, J.-Carlos Baraza-Calvo and Pedro-J. Gil-Vicente has been accepted at IEEE Access. Abstract Reliable computer systems employ error control codes (ECCs) to protect information from errors. For example, memories are frequently protected using single [...]
Presentation at Jornadas SARTECO 2019
Last 18 September, J. Gracia-Morán presented the paper entitled «Mejora de un Código de Corrección de Errores para tolerar fallos adyacentes bidimensionales» at the Jornadas SARTECO 2019.
Panel at CARS 2019
Last September, 17th, Juan Carlos Ruiz took part in the panel «Autonomous driving: safety and security issues», celebrated in the 5th International Workshop on Critical Automotive Applications: Robustness & Safety (CARS 2019), collocated with EDCC 2019 in Naples, Italy.
Presentation at EDCC 2019
Juan Carlos Ruiz has presented the paper entitled «Robustness-aware design space exploration by iteratively augmenting and repairing D-optimal designs», written by Ilya Tuzov, David De Andrés and Juan Carlos Ruiz. Abstract: Design space exploration (DSE) is nowadays of utmost importance to implement HW designs with acceptable levels of performance, power consumption, area and dependability (PPAD). [...]
Paper available at Electronics Journal
The paper entitled “Fault Modeling of Graphene Nanoribbon FET Logic Circuits”, written by D. Gil-Tomàs, J. Gracia-Morán, L.J. Saiz-Adalid and P.J. Gil-Vicente, and published by Electronics Journal, is now available here.
Paper accepted at Electronics Journal
The paper entitled «Fault Modeling of Graphene Nanoribbon FET Logic Circuits», written by D. Gil-Tomàs, J. Gracia-Morán, L.J. Saiz-Adalid and P.J. Gil-Vicente has been accepted for publication at Electronics Journal. Abstract: Due to the increasing defect rates in highly scaled complementary metal–oxide–semiconductor (CMOS) devices, and the emergence of alternative nanotechnology devices, reliability challenges are of [...]
DSN 2020 will be held at UPV
The Fault Tolerant Systems Group (STF) of the Institute ITACA from the UPV will host the next International Conference on Dependable Systems and Networks (DSN), that will be held in Valencia in June 2020. Over the years, the International Conference on Dependable Systems and Networks has pioneered the fusion between dependability and security research, understanding [...]
Paper accepted at Jornadas SARTECO 2019
The paper entitled «Mejora de un Código de Corrección de Errores para tolerar fallos adyacentes bidimensionales» written by J. Gracia-Morán, L.J. Saiz-Adalid, D. Gil-Tomás, J.C. Baraza-Calvo and P.J. Gil-Vicente has been accepted at Jornadas SARTECO 2019. Abstract: Durante estos últimos años, el desarrollo tecnológico ha permitido aumentar la escala de integración de los circuitos integrados. [...]
Paper accepted at ITACA-WIICT 2019
The paper entitled «Comparison of an Improved Matrix-based Error Correction Code», written by J. Gracia-Morán, L.J. Saiz-Adalid, D. Gil-Tomás, J.C. Baraza-Calvo and P.J. Gil-Vicente has been accepted in the Workshop on Innovation on Information and Communication Technologies (ITACA-WIICT 2019). Abstract: Nowadays, the probability of occurrence of Single Cell Upsets (SCUs) or Multiple Cell Upsets (MCUs) [...]
Paper accepted at EDCC 2019
The paper entitled «Robustness-aware design space exploration through iterative refinement of D-optimal designs», written by Ilya Tuzov, David de Andrés and Juan-Carlos Ruiz has been accepted at EDCC 2019. Abstract: Design space exploration (DSE) is nowadays of utmost importance to implement HW designs with acceptable levels of performance, power consumption, area and dependability (PPAD). Electronic [...]