The paper entitled “Comparison of an Improved Matrix-based Error Correction Code”, written by J. Gracia-Morán, L.J. Saiz-Adalid, D. Gil-Tomás, J.C. Baraza-Calvo and P.J. Gil-Vicente has been accepted in the Workshop on Innovation on Information and Communication Technologies (ITACA-WIICT 2019).
Nowadays, the probability of occurrence of Single Cell Upsets (SCUs) or Multiple Cell Upsets (MCUs) has increased due to the continuous in-crement in the integration scale of CMOS technology, that has provoked an augment in the fault rate. SCUs and MCUs are particularly common in comput-er memory systems. To tolerate errors, it is common the use of Error Correction Codes (ECCs). Nevertheless, when using ECCs, a series of overheads are add-ed: extra bits to detect and/or correct errors, and some area, power consumption and delay overheads of the encoders and decoders circuits.
In order to tolerate MCUs, different approaches have been presented in the lit-erature. Specifically, in this work, we present a complete comparison of differ-ent matrix-based ECCs, some of them recently presented.