The paper entitled: “A comparison of two different matrix Error Correction Codes”, written by J. Gracia-Morán, L.J. Saiz-Adalid, D. Gil-Tomás and P.J. Gil-Vicente is availabe at ITACA-WIICT 2018 poceedings.
Due to the continuous increment in the integration scale, the faultrate in computer memory systems has augmented. Thus, the probability of oc-currence of Single Cell Upsets(SCUs) or Multiple Cell Upsets(MCUs) also in-creases. A common solution is the use of Error Correction Codes (ECCs). However, when using ECCs, a good balance between the error coverage, the redundancy introduced and the area, power and delay overheadsof the encoders and decoders circuits must be achieved. In this sense, there exist different proposals to tolerate MCUs. For example, matrix codes are codes able to detect and/or correct MCUs usinga two-dimensional format. However, these codes introduce a great redundancy, which leads to an excessive area, power and delay overhead.In this paper we present a complete comparison of two recently introduced ma-trix codes