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Panel at CARS 2019

Last September, 17th, Juan Carlos Ruiz took part in the panel “Autonomous driving: safety and security issues”, celebrated in the 5th International Workshop on Critical Automotive Applications: Robustness & Safety (CARS 2019), collocated with EDCC 2019 in Naples, Italy.

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Presentation at EDCC 2019

Juan Carlos Ruiz has presented the paper entitled “Robustness-aware design space exploration by iteratively augmenting and repairing D-optimal designs”, written by Ilya Tuzov, David De Andrés and Juan Carlos Ruiz. Abstract: Design space exploration (DSE) is nowadays of utmost importance to implement HW designs with acceptable levels of performance, power consumption, area and dependability (PPAD). [...]

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Paper available at Electronics Journal

The paper entitled “Fault Modeling of Graphene Nanoribbon FET Logic Circuits”, written by D. Gil-Tomàs, J. Gracia-Morán, L.J. Saiz-Adalid and P.J. Gil-Vicente, and published by Electronics Journal, is now available here.  

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Paper accepted at Electronics Journal

The paper entitled “Fault Modeling of Graphene Nanoribbon FET Logic Circuits”, written by D. Gil-Tomàs, J. Gracia-Morán, L.J. Saiz-Adalid and P.J. Gil-Vicente has been accepted for publication at Electronics Journal. Abstract: Due to the increasing defect rates in highly scaled complementary metal–oxide–semiconductor (CMOS) devices, and the emergence of alternative nanotechnology devices, reliability challenges are of [...]

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DSN 2020 will be held at UPV

The Fault Tolerant Systems Group (STF) of the Institute ITACA from the UPV will host the next International Conference on Dependable Systems and Networks (DSN), that will be held in Valencia in June 2020. Over the years, the International Conference on Dependable Systems and Networks has pioneered the fusion between dependability and security research, understanding [...]

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Paper accepted at Jornadas SARTECO 2019

The paper entitled “Mejora de un Código de Corrección de Errores para tolerar fallos adyacentes bidimensionales” written by J. Gracia-Morán, L.J. Saiz-Adalid, D. Gil-Tomás, J.C. Baraza-Calvo and P.J. Gil-Vicente has been accepted at Jornadas SARTECO 2019. Abstract: Durante estos últimos años, el desarrollo tecnológico ha permitido aumentar la escala de integración de los circuitos integrados. [...]

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Paper accepted at ITACA-WIICT 2019

The paper entitled “Comparison of an Improved Matrix-based Error Correction Code”, written by J. Gracia-Morán, L.J. Saiz-Adalid, D. Gil-Tomás, J.C. Baraza-Calvo and P.J. Gil-Vicente has been accepted in the Workshop on Innovation on Information and Communication Technologies (ITACA-WIICT 2019). Abstract: Nowadays, the probability of occurrence of Single Cell Upsets (SCUs) or Multiple Cell Upsets (MCUs) [...]

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Paper accepted at EDCC 2019

The paper entitled “Robustness-aware design space exploration through iterative refinement of D-optimal designs”, written by Ilya Tuzov, David de Andrés and Juan-Carlos Ruiz has been accepted at EDCC 2019. Abstract: Design space exploration (DSE) is nowadays of utmost importance to implement HW designs with acceptable levels of performance, power consumption, area and dependability (PPAD).  Electronic [...]

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Paper published at ITACA-WIICT 2018 (III)

The paper entitled: “Towards dependability-aware design space exploration using genetic algorithms”, written by Quentin Fabry, Ilya Tuzov, Juan-Carlos Ruiz and David de Andres is availabe at ITACA-WIICT 2018 poceedings. Abstract: The development of complex digital systems poses some design optimization problems that are today automatically addressed by Electronic Design Automation (EDA) tools. Deducing optimal configurations for [...]

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Paper published at ITACA-WIICT 2018 (II)

The paper entitled: “Energy-aware Design Space Exploration for Optimal Implementation Parameters Tuning”, written by Ilya Tuzov, David de Andrés, and Juan Carlos Ruiz is availabe at ITACA-WIICT 2018 poceedings. Abstract: Determining the optimum configuration of semicustom implementation tools to simultaneously optimize the energy consumption, maximum clock frequency, and area of the target circuit requires navigating through [...]

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