Presentation at Jornadas SARTECO 2019
Last 18 September, J. Gracia-Morán presented the paper entitled “Mejora de un Código de Corrección de Errores para tolerar fallos adyacentes bidimensionales” at the Jornadas SARTECO 2019.
Paper accepted at Jornadas SARTECO 2019
The paper entitled “Mejora de un Código de Corrección de Errores para tolerar fallos adyacentes bidimensionales” written by J. Gracia-Morán, L.J. Saiz-Adalid, D. Gil-Tomás, J.C. Baraza-Calvo and P.J. Gil-Vicente has been accepted at Jornadas SARTECO 2019. Abstract: Durante estos últimos años, el desarrollo tecnológico ha permitido aumentar la escala de integración de los circuitos integrados. [...]
Paper accepted at ITACA-WIICT 2019
The paper entitled “Comparison of an Improved Matrix-based Error Correction Code”, written by J. Gracia-Morán, L.J. Saiz-Adalid, D. Gil-Tomás, J.C. Baraza-Calvo and P.J. Gil-Vicente has been accepted in the Workshop on Innovation on Information and Communication Technologies (ITACA-WIICT 2019). Abstract: Nowadays, the probability of occurrence of Single Cell Upsets (SCUs) or Multiple Cell Upsets (MCUs) [...]
Paper published at ITACA-WIICT 2018 (III)
The paper entitled: “Towards dependability-aware design space exploration using genetic algorithms”, written by Quentin Fabry, Ilya Tuzov, Juan-Carlos Ruiz and David de Andres is availabe at ITACA-WIICT 2018 poceedings. Abstract: The development of complex digital systems poses some design optimization problems that are today automatically addressed by Electronic Design Automation (EDA) tools. Deducing optimal configurations for [...]
Paper published at ITACA-WIICT 2018 (II)
The paper entitled: “Energy-aware Design Space Exploration for Optimal Implementation Parameters Tuning”, written by Ilya Tuzov, David de Andrés, and Juan Carlos Ruiz is availabe at ITACA-WIICT 2018 poceedings. Abstract: Determining the optimum configuration of semicustom implementation tools to simultaneously optimize the energy consumption, maximum clock frequency, and area of the target circuit requires navigating through [...]
Paper published at ITACA-WIICT 2018 (I)
The paper entitled: “A comparison of two different matrix Error Correction Codes”, written by J. Gracia-Morán, L.J. Saiz-Adalid, D. Gil-Tomás and P.J. Gil-Vicente is availabe at ITACA-WIICT 2018 poceedings. Abstract: Due to the continuous increment in the integration scale, the faultrate in computer memory systems has augmented. Thus, the probability of oc-currence of Single Cell [...]
Presentation at Jornadas Sarteco
J. Gracia-Morán has presented the paper entitled “Un nuevo Código de Corrección de Errores matricial con baja redundancia“, presented at the Jornadas Sarteco, held in Teruel, 12-14 September, 2018.
Paper accepted at WIICT 2018 (III)
The paper entitled “Towards dependability-aware design space exploration using genetic algorithms” written by Quentin Fabry, Ilya Tuzov, Juan-Carlos Ruiz and David de Andrés has been accepted in the Workshop on Innovation on Information and Communication Technologies (ITACA-WIICT 2018) Abstract: The development of complex digital systems poses some design optimization problems that are today automatically addressed [...]
Paper accepted at WIICT 2018 (II)
The paper entitled “Energy-aware Design Space Exploration for Optimal Implementation Parameters Tuning” written by Ilya Tuzov, David de Andrés and Juan Carlos Ruiz has been accepted in the Workshop on Innovation on Information and Communication Technologies (ITACA-WIICT 2018) Abstract: Determining the optimum configuration of semicustom implementation tools to simultaneously optimize the energy consumption, maximum clock [...]
Paper accepted at WIICT 2018
The paper entitled “A comparison of two different matrix Error Correction Codes” written by J. Gracia-Morán, L.J. Saiz-Adalid, D. Gil-Tomás and P.J. Gil-Vicente has been accepted in the Workshop on Innovation on Information and Communication Technologies (ITACA-WIICT 2018) Abstract: Due to the continuous increment in the integration scale, the fault rate in computer memory systems [...]